PPCArch.h File Reference

#include "dolphin/types.h"

Go to the source code of this file.

Data Structures
struct	PPC_GQR_t
union	PPC_GQR_u
struct	PPC_DMA_U_t
union	PPC_DMA_U_u
struct	PPC_DMA_L_t
union	PPC_DMA_L_u

Macros
#define	CTR   9
#define	XER   1
#define	LR   8
#define	UPMC1   937
#define	UPMC2   938
#define	UPMC3   941
#define	UPMC4   942
#define	USIA   939
#define	UMMCR0   936
#define	UMMCR1   940
#define	HID0   1008
#define	HID1   1009
#define	PVR   287
#define	IBAT0U   528
#define	IBAT0L   529
#define	IBAT1U   530
#define	IBAT1L   531
#define	IBAT2U   532
#define	IBAT2L   533
#define	IBAT3U   534
#define	IBAT3L   535
#define	DBAT0U   536
#define	DBAT0L   537
#define	DBAT1U   538
#define	DBAT1L   539
#define	DBAT2U   540
#define	DBAT2L   541
#define	DBAT3U   542
#define	DBAT3L   543
#define	SDR1   25
#define	SPRG0   272
#define	SPRG1   273
#define	SPRG2   274
#define	SPRG3   275
#define	DAR   19
#define	DSISR   18
#define	SRR0   26
#define	SRR1   27
#define	EAR   282
#define	DABR   1013
#define	TBL   284
#define	TBU   285
#define	L2CR   1017
#define	DEC   22
#define	IABR   1010
#define	PMC1   953
#define	PMC2   954
#define	PMC3   957
#define	PMC4   958
#define	SIA   955
#define	MMCR0   952
#define	MMCR1   956
#define	THRM1   1020
#define	THRM2   1021
#define	THRM3   1022
#define	ICTC   1019
#define	GQR0   912
#define	GQR1   913
#define	GQR2   914
#define	GQR3   915
#define	GQR4   916
#define	GQR5   917
#define	GQR6   918
#define	GQR7   919
#define	HID2   920
#define	WPAR   921
#define	DMA_U   922
#define	DMA_L   923
#define	MSR_POW   0x00040000
#define	MSR_ILE   0x00010000
#define	MSR_EE   0x00008000
#define	MSR_PR   0x00004000
#define	MSR_FP   0x00002000
#define	MSR_ME   0x00001000
#define	MSR_FE0   0x00000800
#define	MSR_SE   0x00000400
#define	MSR_BE   0x00000200
#define	MSR_FE1   0x00000100
#define	MSR_IP   0x00000040
#define	MSR_IR   0x00000020
#define	MSR_DR   0x00000010
#define	MSR_PM   0x00000004
#define	MSR_RI   0x00000002
#define	MSR_LE   0x00000001
#define	MSR_POW_BIT   13
#define	MSR_ILE_BIT   15
#define	MSR_EE_BIT   16
#define	MSR_PR_BIT   17
#define	MSR_FP_BIT   18
#define	MSR_ME_BIT   19
#define	MSR_FE0_BIT   20
#define	MSR_SE_BIT   21
#define	MSR_BE_BIT   22
#define	MSR_FE1_BIT   23
#define	MSR_IP_BIT   25
#define	MSR_IR_BIT   26
#define	MSR_DR_BIT   27
#define	MSR_PM_BIT   29
#define	MSR_RI_BIT   30
#define	MSR_LE_BIT   31
#define	HID0_EMCP   0x80000000u
#define	HID0_DBP   0x40000000u
#define	HID0_EBA   0x20000000u
#define	HID0_EBD   0x10000000u
#define	HID0_BCLK   0x08000000u
#define	HID0_ECLK   0x02000000u
#define	HID0_PAR   0x01000000u
#define	HID0_DOZE   0x00800000u
#define	HID0_NAP   0x00400000u
#define	HID0_SLEEP   0x00200000u
#define	HID0_DPM   0x00100000u
#define	HID0_NHR   0x00010000u
#define	HID0_ICE   0x00008000u
#define	HID0_DCE   0x00004000u
#define	HID0_ILOCK   0x00002000u
#define	HID0_DLOCK   0x00001000u
#define	HID0_ICFI   0x00000800u
#define	HID0_DCFI   0x00000400u
#define	HID0_SPD   0x00000200u
#define	HID0_IFEM   0x00000100u
#define	HID0_SGE   0x00000080u
#define	HID0_DCFA   0x00000040u
#define	HID0_BTIC   0x00000020u
#define	HID0_ABE   0x00000008u
#define	HID0_BHT   0x00000004u
#define	HID0_NOOPTI   0x00000001u
#define	HID0_ICE_BIT   16
#define	HID0_DCE_BIT   17
#define	HID0_ILOCK_BIT   18
#define	HID0_DLOCK_BIT   19
#define	HID2_LSQE   0x80000000
#define	HID2_WPE   0x40000000
#define	HID2_PSE   0x20000000
#define	HID2_LCE   0x10000000
#define	HID2_DCHERR   0x00800000
#define	HID2_DNCERR   0x00400000
#define	HID2_DCMERR   0x00200000
#define	HID2_DQOERR   0x00100000
#define	HID2_DCHEE   0x00080000
#define	HID2_DNCEE   0x00040000
#define	HID2_DCMEE   0x00020000
#define	HID2_DQOEE   0x00010000
#define	HID2_DMAQL_MASK   0x0F000000
#define	HID2_DMAQL_SHIFT   24
#define	HID2_LSQE_BIT   0
#define	HID2_WPE_BIT   1
#define	HID2_PSE_BIT   2
#define	HID2_LCE_BIT   3
#define	HID2_DCHERR_BIT   8
#define	HID2_DNCERR_BIT   9
#define	HID2_DCMERR_BIT   10
#define	HID2_DQOERR_BIT   11
#define	HID2_DCHEE_BIT   12
#define	HID2_DNCEE_BIT   13
#define	HID2_DCMEE_BIT   14
#define	HID2_DQOEE_BIT   15
#define	GQR_LOAD_SCALE_MASK   0x3F000000
#define	GQR_LOAD_TYPE_MASK   0x00070000
#define	GQR_STORE_SCALE_MASK   0x00003F00
#define	GQR_STORE_TYPE_MASK   0x00000007
#define	DMA_U_ADDR_MASK   0xFFFFFFE0
#define	DMA_U_LEN_U_MASK   0x0000001F
#define	DMA_L_LC_ADDR_MASK   0xFFFFFFE0
#define	DMA_L_LOAD   0x00000010
#define	DMA_L_STORE   0x00000000
#define	DMA_L_LEN_MASK   0x0000000C
#define	DMA_L_TRIGGER   0x00000002
#define	DMA_L_FLUSH   0x00000001
#define	WPAR_ADDR   0xFFFFFFE0
#define	WPAR_BNE   0x00000001
#define	SRR1_DMA_BIT   0x00200000
#define	SRR1_L2DP_BIT   0x00100000
#define	L2CR_L2E   0x80000000
#define	L2CR_L2PE   0x40000000
#define	L2CR_L2SIZ_256K   0x10000000
#define	L2CR_L2SIZ_512K   0x20000000
#define	L2CR_L2SIZ_1M   0x30000000
#define	L2CR_L2CLK_1_0   0x02000000
#define	L2CR_L2CLK_1_5   0x04000000
#define	L2CR_L2CLK_2_0   0x08000000
#define	L2CR_L2CLK_2_5   0x0A000000
#define	L2CR_L2CLK_3_0   0x0C000000
#define	L2CR_RAM_FLOW_THRU_BURST   0x00000000
#define	L2CR_RAM_PIPELINE_BURST   0x01000000
#define	L2CR_RAM_PIPELINE_LATE   0x01800000
#define	L2CR_L2DO   0x00400000
#define	L2CR_L2I   0x00200000
#define	L2CR_L2CTL   0x00100000
#define	L2CR_L2WT   0x00080000
#define	L2CR_L2TS   0x00040000
#define	L2CR_L2OH_0_5   0x00000000
#define	L2CR_L2OH_1_0   0x00010000
#define	L2CR_L2SL   0x00008000
#define	L2CR_L2DF   0x00004000
#define	L2CR_L2BYP   0x00002000
#define	L2CR_L2CS   0x00000200
#define	L2CR_L2DRO   0x00000100
#define	L2CR_L2CTR_MASK   0x000000FE
#define	L2CR_L2IP   0x00000001
#define	MMCR0_DIS   0x80000000
#define	MMCR0_DP   0x40000000
#define	MMCR0_DU   0x20000000
#define	MMCR0_DMS   0x10000000
#define	MMCR0_DMR   0x08000000
#define	MMCR0_ENINT   0x04000000
#define	MMCR0_DISCOUNT   0x02000000
#define	MMCR0_RTCSELECT_MASK   0x01800000
#define	MMCR0_RTCSELECT_63   0x00000000
#define	MMCR0_RTCSELECT_55   0x00800000
#define	MMCR0_RTCSELECT_51   0x01000000
#define	MMCR0_RTCSELECT_47   0x01800000
#define	MMCR0_INTONBITTRANS   0x00400000
#define	MMCR0_THRESHOLD_MASK   0x003F0000
#define	MMCR0_THRESHOLD(n)
#define	MMCR0_PMC1INTCONTROL   0x00008000
#define	MMCR0_PMC2INTCONTROL   0x00004000
#define	MMCR0_PMCTRIGGER   0x00002000
#define	MMCR0_PMC1SELECT_MASK   0x00001FC0
#define	MMCR0_PMC2SELECT_MASK   0x0000003F
#define	MMCR1_PMC3SELECT_MASK   0xF8000000
#define	MMCR1_PMC4SELECT_MASK   0x07C00000
#define	PMC1_OV   0x80000000
#define	PMC1_COUNTER   0x7FFFFFFF
#define	PMC2_OV   0x80000000
#define	PMC2_COUNTER   0x7FFFFFFF
#define	PMC3_OV   0x80000000
#define	PMC3_COUNTER   0x7FFFFFFF
#define	PMC4_OV   0x80000000
#define	PMC4_COUNTER   0x7FFFFFFF
#define	MMCR0_PMC1_HOLD   0x00000000
#define	MMCR0_PMC1_CYCLE   0x00000040
#define	MMCR0_PMC1_INSTRUCTION   0x00000080
#define	MMCR0_PMC1_TRANSITION   0x000000C0
#define	MMCR0_PMC1_DISPATCHED   0x00000100
#define	MMCR0_PMC1_EIEIO   0x00000140
#define	MMCR0_PMC1_ITLB_CYCLE   0x00000180
#define	MMCR0_PMC1_L2_HIT   0x000001C0
#define	MMCR0_PMC1_EA   0x00000200
#define	MMCR0_PMC1_IABR   0x00000240
#define	MMCR0_PMC1_L1_MISS   0x00000280
#define	MMCR0_PMC1_Bx_UNRESOLVED   0x000002C0
#define	MMCR0_PMC1_Bx_STALL_CYCLE   0x00000300
#define	MMCR0_PMC1_IC_FETCH_MISS   0x00000340
#define	MMCR0_PMC2_HOLD   0x00000000
#define	MMCR0_PMC2_CYCLE   0x00000001
#define	MMCR0_PMC2_INSTRUCTION   0x00000002
#define	MMCR0_PMC2_TRANSITION   0x00000003
#define	MMCR0_PMC2_DISPATCHED   0x00000004
#define	MMCR0_PMC2_IC_MISS   0x00000005
#define	MMCR0_PMC2_ITLB_MISS   0x00000006
#define	MMCR0_PMC2_L2_I_MISS   0x00000007
#define	MMCR0_PMC2_Bx_FALL_TROUGH   0x00000008
#define	MMCR0_PMC2_PR_SWITCH   0x00000009
#define	MMCR0_PMC2_RESERVED_LOAD   0x0000000A
#define	MMCR0_PMC2_LOAD_STORE   0x0000000B
#define	MMCR0_PMC2_SNOOP   0x0000000C
#define	MMCR0_PMC2_L1_CASTOUT   0x0000000D
#define	MMCR0_PMC2_SYSTEM   0x0000000E
#define	MMCR0_PMC2_IC_FETCH_MISS   0x0000000F
#define	MMCR0_PMC2_Bx_OUT_OF_ORDER   0x00000010
#define	MMCR1_PMC3_HOLD   0x00000000
#define	MMCR1_PMC3_CYCLE   0x08000000
#define	MMCR1_PMC3_INSTRUCTION   0x10000000
#define	MMCR1_PMC3_TRANSITION   0x18000000
#define	MMCR1_PMC3_DISPATCHED   0x20000000
#define	MMCR1_PMC3_DC_MISS   0x28000000
#define	MMCR1_PMC3_DTLB_MISS   0x30000000
#define	MMCR1_PMC3_L2_D_MISS   0x38000000
#define	MMCR1_PMC3_Bx_TAKEN   0x40000000
#define	MMCR1_PMC3_PM_SWITCH   0x48000000
#define	MMCR1_PMC3_COND_STORE   0x50000000
#define	MMCR1_PMC3_FPU   0x58000000
#define	MMCR1_PMC3_L2_SNOOP_CASTOUT   0x60000000
#define	MMCR1_PMC3_L2_HIT   0x68000000
#define	MMCR1_PMC3_L1_MISS_CYCLE   0x78000000
#define	MMCR1_PMC3_Bx_SECOND   0x80000000
#define	MMCR1_PMC3_BPU_LR_CR   0x88000000
#define	MMCR1_PMC4_HOLD   0x00000000
#define	MMCR1_PMC4_CYCLE   0x00400000
#define	MMCR1_PMC4_INSTRUCTION   0x00800000
#define	MMCR1_PMC4_TRANSITION   0x00C00000
#define	MMCR1_PMC4_DISPATCHED   0x01000000
#define	MMCR1_PMC4_L2_CASTOUT   0x01400000
#define	MMCR1_PMC4_DTLB_CYCLE   0x01800000
#define	MMCR1_PMC4_Bx_MISSED   0x02000000
#define	MMCR1_PMC4_COND_STORE_INT   0x02800000
#define	MMCR1_PMC4_SYNC   0x02C00000
#define	MMCR1_PMC4_SNOOP_RETRY   0x03000000
#define	MMCR1_PMC4_INTEGER   0x03400000
#define	MMCR1_PMC4_BPU_THIRD   0x03800000
#define	MMCR1_PMC4_DC_MISS   0x07C00000
#define	FPSCR_FX   0x80000000
#define	FPSCR_FEX   0x40000000
#define	FPSCR_VX   0x20000000
#define	FPSCR_OX   0x10000000
#define	FPSCR_UX   0x08000000
#define	FPSCR_ZX   0x04000000
#define	FPSCR_XX   0x02000000
#define	FPSCR_VXSNAN   0x01000000
#define	FPSCR_VXISI   0x00800000
#define	FPSCR_VXIDI   0x00400000
#define	FPSCR_VXZDZ   0x00200000
#define	FPSCR_VXIMZ   0x00100000
#define	FPSCR_VXVC   0x00080000
#define	FPSCR_FR   0x00040000
#define	FPSCR_FI   0x00020000
#define	FPSCR_VXSOFT   0x00000400
#define	FPSCR_VXSQRT   0x00000200
#define	FPSCR_VXCVI   0x00000100
#define	FPSCR_VE   0x00000080
#define	FPSCR_OE   0x00000040
#define	FPSCR_UE   0x00000020
#define	FPSCR_ZE   0x00000010
#define	FPSCR_XE   0x00000008
#define	FPSCR_NI   0x00000004
#define	FPSCR_FX_BIT   0
#define	FPSCR_FEX_BIT   1
#define	FPSCR_VX_BIT   2
#define	FPSCR_OX_BIT   3
#define	FPSCR_UX_BIT   4
#define	FPSCR_ZX_BIT   5
#define	FPSCR_XX_BIT   6
#define	FPSCR_VXSNAN_BIT   7
#define	FPSCR_VXISI_BIT   8
#define	FPSCR_VXIDI_BIT   9
#define	FPSCR_VXZDZ_BIT   10
#define	FPSCR_VXIMZ_BIT   11
#define	FPSCR_VXVC_BIT   12
#define	FPSCR_FR_BIT   13
#define	FPSCR_FI_BIT   14
#define	FPSCR_VXSOFT_BIT   21
#define	FPSCR_VXSQRT_BIT   22
#define	FPSCR_VXCVI_BIT   23
#define	FPSCR_VE_BIT   24
#define	FPSCR_OE_BIT   25
#define	FPSCR_UE_BIT   26
#define	FPSCR_ZE_BIT   27
#define	FPSCR_XE_BIT   28
#define	FPSCR_NI_BIT   29

Functions
u32	PPCMfmsr ()
void	PPCMtmsr (u32 newMSR)
u32	PPCOrMsr (u32 value)
u32	PPCMfhid0 ()
void	PPCMthid0 (u32 newHID0)
u32	PPCMfl2cr ()
void	PPCMtl2cr (u32 newL2cr)
void	PPCMtdec (u32 newDec)
void	PPCSync ()
void	PPCHalt ()
u32	PPCMffpscr ()
void	PPCMtfpscr (u32 newFPSCR)
u32	PPCMfhid2 ()
void	PPCMthid2 (u32 newhid2)
u32	PPCMfwpar ()
void	PPCMtwpar (u32 newwpar)
void	PPCEnableSpeculation ()
void	PPCDisableSpeculation ()
void	PPCSetFpIEEEMode ()
void	PPCSetFpNonIEEEMode ()
u32	PPCMfpmc4 ()
u32	PPCMfpmc3 ()
u32	PPCMfpmc1 ()
void	PPCMtpmc1 (u32 newPmc1)
void	PPCMtpmc2 (u32 newPmc1)
void	PPCMtpmc3 (u32 newPmc1)
void	PPCMtpmc4 (u32 newPmc1)
void	PPCMtmmcr0 (u32 newMmcr0)
void	PPCMtmmcr1 (u32 newMmcr0)
void	PPCMtdmaU (u32 newdmau)
void	PPCMtdmaL (u32 newdmal)
u32	PPCMfdec (void)
u32	PPCAndMsr (u32 value)
u32	PPCAndCMsr (u32 value)
u32	PPCMfhid1 ()
void	PPCEieio ()
u32	PPCMfmmcr0 ()
u32	PPCMfmmcr1 ()
u32	PPCMfpmc2 ()
u32	PPCMfsia ()
void	PPCMtsia (u32 newSia)
u32	PPCMfdmaL ()
u32	PPCMfpvr ()
u32	PPCMfdmaU ()
void	PMBegin (void)
void	PMEnd (void)
void	PMCycles (void)
void	PML1FetchMisses (void)
void	PML1MissCycles (void)
void	PMInstructions (void)

Macro Definition Documentation

CTR

#define CTR   9

XER

#define XER   1

LR

#define LR   8

UPMC1

#define UPMC1   937

UPMC2

#define UPMC2   938

UPMC3

#define UPMC3   941

UPMC4

#define UPMC4   942

USIA

#define USIA   939

UMMCR0

#define UMMCR0   936

UMMCR1

#define UMMCR1   940

HID0

#define HID0   1008

HID1

#define HID1   1009

PVR

#define PVR   287

IBAT0U

#define IBAT0U   528

IBAT0L

#define IBAT0L   529

IBAT1U

#define IBAT1U   530

IBAT1L

#define IBAT1L   531

IBAT2U

#define IBAT2U   532

IBAT2L

#define IBAT2L   533

IBAT3U

#define IBAT3U   534

IBAT3L

#define IBAT3L   535

DBAT0U

#define DBAT0U   536

DBAT0L

#define DBAT0L   537

DBAT1U

#define DBAT1U   538

DBAT1L

#define DBAT1L   539

DBAT2U

#define DBAT2U   540

DBAT2L

#define DBAT2L   541

DBAT3U

#define DBAT3U   542

DBAT3L

#define DBAT3L   543

SDR1

#define SDR1   25

SPRG0

#define SPRG0   272

SPRG1

#define SPRG1   273

SPRG2

#define SPRG2   274

SPRG3

#define SPRG3   275

DAR

#define DAR   19

DSISR

#define DSISR   18

SRR0

#define SRR0   26

SRR1

#define SRR1   27

EAR

#define EAR   282

DABR

#define DABR   1013

TBL

#define TBL   284

TBU

#define TBU   285

L2CR

#define L2CR   1017

DEC

#define DEC   22

IABR

#define IABR   1010

PMC1

#define PMC1   953

PMC2

#define PMC2   954

PMC3

#define PMC3   957

PMC4

#define PMC4   958

SIA

#define SIA   955

MMCR0

#define MMCR0   952

MMCR1

#define MMCR1   956

THRM1

#define THRM1   1020

THRM2

#define THRM2   1021

THRM3

#define THRM3   1022

ICTC

#define ICTC   1019

GQR0

#define GQR0   912

GQR1

#define GQR1   913

GQR2

#define GQR2   914

GQR3

#define GQR3   915

GQR4

#define GQR4   916

GQR5

#define GQR5   917

GQR6

#define GQR6   918

GQR7

#define GQR7   919

HID2

#define HID2   920

WPAR

#define WPAR   921

DMA_U

#define DMA_U   922

DMA_L

#define DMA_L   923

MSR_POW

#define MSR_POW   0x00040000

MSR_ILE

#define MSR_ILE   0x00010000

MSR_EE

#define MSR_EE   0x00008000

MSR_PR

#define MSR_PR   0x00004000

MSR_FP

#define MSR_FP   0x00002000

MSR_ME

#define MSR_ME   0x00001000

MSR_FE0

#define MSR_FE0   0x00000800

MSR_SE

#define MSR_SE   0x00000400

MSR_BE

#define MSR_BE   0x00000200

MSR_FE1

#define MSR_FE1   0x00000100

MSR_IP

#define MSR_IP   0x00000040

MSR_IR

#define MSR_IR   0x00000020

MSR_DR

#define MSR_DR   0x00000010

MSR_PM

#define MSR_PM   0x00000004

MSR_RI

#define MSR_RI   0x00000002

MSR_LE

#define MSR_LE   0x00000001

MSR_POW_BIT

#define MSR_POW_BIT   13

MSR_ILE_BIT

#define MSR_ILE_BIT   15

MSR_EE_BIT

#define MSR_EE_BIT   16

MSR_PR_BIT

#define MSR_PR_BIT   17

MSR_FP_BIT

#define MSR_FP_BIT   18

MSR_ME_BIT

#define MSR_ME_BIT   19

MSR_FE0_BIT

#define MSR_FE0_BIT   20

MSR_SE_BIT

#define MSR_SE_BIT   21

MSR_BE_BIT

#define MSR_BE_BIT   22

MSR_FE1_BIT

#define MSR_FE1_BIT   23

MSR_IP_BIT

#define MSR_IP_BIT   25

MSR_IR_BIT

#define MSR_IR_BIT   26

MSR_DR_BIT

#define MSR_DR_BIT   27

MSR_PM_BIT

#define MSR_PM_BIT   29

MSR_RI_BIT

#define MSR_RI_BIT   30

MSR_LE_BIT

#define MSR_LE_BIT   31

HID0_EMCP

#define HID0_EMCP   0x80000000u

HID0_DBP

#define HID0_DBP   0x40000000u

HID0_EBA

#define HID0_EBA   0x20000000u

HID0_EBD

#define HID0_EBD   0x10000000u

HID0_BCLK

#define HID0_BCLK   0x08000000u

HID0_ECLK

#define HID0_ECLK   0x02000000u

HID0_PAR

#define HID0_PAR   0x01000000u

HID0_DOZE

#define HID0_DOZE   0x00800000u

HID0_NAP

#define HID0_NAP   0x00400000u

HID0_SLEEP

#define HID0_SLEEP   0x00200000u

HID0_DPM

#define HID0_DPM   0x00100000u

HID0_NHR

#define HID0_NHR   0x00010000u

HID0_ICE

#define HID0_ICE   0x00008000u

HID0_DCE

#define HID0_DCE   0x00004000u

HID0_ILOCK

#define HID0_ILOCK   0x00002000u

HID0_DLOCK

#define HID0_DLOCK   0x00001000u

HID0_ICFI

#define HID0_ICFI   0x00000800u

HID0_DCFI

#define HID0_DCFI   0x00000400u

HID0_SPD

#define HID0_SPD   0x00000200u

HID0_IFEM

#define HID0_IFEM   0x00000100u

HID0_SGE

#define HID0_SGE   0x00000080u

HID0_DCFA

#define HID0_DCFA   0x00000040u

HID0_BTIC

#define HID0_BTIC   0x00000020u

HID0_ABE

#define HID0_ABE   0x00000008u

HID0_BHT

#define HID0_BHT   0x00000004u

HID0_NOOPTI

#define HID0_NOOPTI   0x00000001u

HID0_ICE_BIT

#define HID0_ICE_BIT   16

HID0_DCE_BIT

#define HID0_DCE_BIT   17

HID0_ILOCK_BIT

#define HID0_ILOCK_BIT   18

HID0_DLOCK_BIT

#define HID0_DLOCK_BIT   19

HID2_LSQE

#define HID2_LSQE   0x80000000

HID2_WPE

#define HID2_WPE   0x40000000

HID2_PSE

#define HID2_PSE   0x20000000

HID2_LCE

#define HID2_LCE   0x10000000

HID2_DCHERR

#define HID2_DCHERR   0x00800000

HID2_DNCERR

#define HID2_DNCERR   0x00400000

HID2_DCMERR

#define HID2_DCMERR   0x00200000

HID2_DQOERR

#define HID2_DQOERR   0x00100000

HID2_DCHEE

#define HID2_DCHEE   0x00080000

HID2_DNCEE

#define HID2_DNCEE   0x00040000

HID2_DCMEE

#define HID2_DCMEE   0x00020000

HID2_DQOEE

#define HID2_DQOEE   0x00010000

HID2_DMAQL_MASK

#define HID2_DMAQL_MASK   0x0F000000

HID2_DMAQL_SHIFT

#define HID2_DMAQL_SHIFT   24

HID2_LSQE_BIT

#define HID2_LSQE_BIT   0

HID2_WPE_BIT

#define HID2_WPE_BIT   1

HID2_PSE_BIT

#define HID2_PSE_BIT   2

HID2_LCE_BIT

#define HID2_LCE_BIT   3

HID2_DCHERR_BIT

#define HID2_DCHERR_BIT   8

HID2_DNCERR_BIT

#define HID2_DNCERR_BIT   9

HID2_DCMERR_BIT

#define HID2_DCMERR_BIT   10

HID2_DQOERR_BIT

#define HID2_DQOERR_BIT   11

HID2_DCHEE_BIT

#define HID2_DCHEE_BIT   12

HID2_DNCEE_BIT

#define HID2_DNCEE_BIT   13

HID2_DCMEE_BIT

#define HID2_DCMEE_BIT   14

HID2_DQOEE_BIT

#define HID2_DQOEE_BIT   15

GQR_LOAD_SCALE_MASK

#define GQR_LOAD_SCALE_MASK   0x3F000000

GQR_LOAD_TYPE_MASK

#define GQR_LOAD_TYPE_MASK   0x00070000

GQR_STORE_SCALE_MASK

#define GQR_STORE_SCALE_MASK   0x00003F00

GQR_STORE_TYPE_MASK

#define GQR_STORE_TYPE_MASK   0x00000007

DMA_U_ADDR_MASK

#define DMA_U_ADDR_MASK   0xFFFFFFE0

DMA_U_LEN_U_MASK

#define DMA_U_LEN_U_MASK   0x0000001F

DMA_L_LC_ADDR_MASK

#define DMA_L_LC_ADDR_MASK   0xFFFFFFE0

DMA_L_LOAD

#define DMA_L_LOAD   0x00000010

DMA_L_STORE

#define DMA_L_STORE   0x00000000

DMA_L_LEN_MASK

#define DMA_L_LEN_MASK   0x0000000C

DMA_L_TRIGGER

#define DMA_L_TRIGGER   0x00000002

DMA_L_FLUSH

#define DMA_L_FLUSH   0x00000001

WPAR_ADDR

#define WPAR_ADDR   0xFFFFFFE0

WPAR_BNE

#define WPAR_BNE   0x00000001

SRR1_DMA_BIT

#define SRR1_DMA_BIT   0x00200000

SRR1_L2DP_BIT

#define SRR1_L2DP_BIT   0x00100000

L2CR_L2E

#define L2CR_L2E   0x80000000

L2CR_L2PE

#define L2CR_L2PE   0x40000000

L2CR_L2SIZ_256K

#define L2CR_L2SIZ_256K   0x10000000

L2CR_L2SIZ_512K

#define L2CR_L2SIZ_512K   0x20000000

L2CR_L2SIZ_1M

#define L2CR_L2SIZ_1M   0x30000000

L2CR_L2CLK_1_0

#define L2CR_L2CLK_1_0   0x02000000

L2CR_L2CLK_1_5

#define L2CR_L2CLK_1_5   0x04000000

L2CR_L2CLK_2_0

#define L2CR_L2CLK_2_0   0x08000000

L2CR_L2CLK_2_5

#define L2CR_L2CLK_2_5   0x0A000000

L2CR_L2CLK_3_0

#define L2CR_L2CLK_3_0   0x0C000000

L2CR_RAM_FLOW_THRU_BURST

#define L2CR_RAM_FLOW_THRU_BURST   0x00000000

L2CR_RAM_PIPELINE_BURST

#define L2CR_RAM_PIPELINE_BURST   0x01000000

L2CR_RAM_PIPELINE_LATE

#define L2CR_RAM_PIPELINE_LATE   0x01800000

L2CR_L2DO

#define L2CR_L2DO   0x00400000

L2CR_L2I

#define L2CR_L2I   0x00200000

L2CR_L2CTL

#define L2CR_L2CTL   0x00100000

L2CR_L2WT

#define L2CR_L2WT   0x00080000

L2CR_L2TS

#define L2CR_L2TS   0x00040000

L2CR_L2OH_0_5

#define L2CR_L2OH_0_5   0x00000000

L2CR_L2OH_1_0

#define L2CR_L2OH_1_0   0x00010000

L2CR_L2SL

#define L2CR_L2SL   0x00008000

L2CR_L2DF

#define L2CR_L2DF   0x00004000

L2CR_L2BYP

#define L2CR_L2BYP   0x00002000

L2CR_L2CS

#define L2CR_L2CS   0x00000200

L2CR_L2DRO

#define L2CR_L2DRO   0x00000100

L2CR_L2CTR_MASK

#define L2CR_L2CTR_MASK   0x000000FE

L2CR_L2IP

#define L2CR_L2IP   0x00000001

MMCR0_DIS

#define MMCR0_DIS   0x80000000

MMCR0_DP

#define MMCR0_DP   0x40000000

MMCR0_DU

#define MMCR0_DU   0x20000000

MMCR0_DMS

#define MMCR0_DMS   0x10000000

MMCR0_DMR

#define MMCR0_DMR   0x08000000

MMCR0_ENINT

#define MMCR0_ENINT   0x04000000

MMCR0_DISCOUNT

#define MMCR0_DISCOUNT   0x02000000

MMCR0_RTCSELECT_MASK

#define MMCR0_RTCSELECT_MASK   0x01800000

MMCR0_RTCSELECT_63

#define MMCR0_RTCSELECT_63   0x00000000

MMCR0_RTCSELECT_55

#define MMCR0_RTCSELECT_55   0x00800000

MMCR0_RTCSELECT_51

#define MMCR0_RTCSELECT_51   0x01000000

MMCR0_RTCSELECT_47

#define MMCR0_RTCSELECT_47   0x01800000

MMCR0_INTONBITTRANS

#define MMCR0_INTONBITTRANS   0x00400000

MMCR0_THRESHOLD_MASK

#define MMCR0_THRESHOLD_MASK   0x003F0000

MMCR0_THRESHOLD

#define MMCR0_THRESHOLD

(

n

)

Value:

((n) << 16)

MMCR0_PMC1INTCONTROL

#define MMCR0_PMC1INTCONTROL   0x00008000

MMCR0_PMC2INTCONTROL

#define MMCR0_PMC2INTCONTROL   0x00004000

MMCR0_PMCTRIGGER

#define MMCR0_PMCTRIGGER   0x00002000

MMCR0_PMC1SELECT_MASK

#define MMCR0_PMC1SELECT_MASK   0x00001FC0

MMCR0_PMC2SELECT_MASK

#define MMCR0_PMC2SELECT_MASK   0x0000003F

MMCR1_PMC3SELECT_MASK

#define MMCR1_PMC3SELECT_MASK   0xF8000000

MMCR1_PMC4SELECT_MASK

#define MMCR1_PMC4SELECT_MASK   0x07C00000

PMC1_OV

#define PMC1_OV   0x80000000

PMC1_COUNTER

#define PMC1_COUNTER   0x7FFFFFFF

PMC2_OV

#define PMC2_OV   0x80000000

PMC2_COUNTER

#define PMC2_COUNTER   0x7FFFFFFF

PMC3_OV

#define PMC3_OV   0x80000000

PMC3_COUNTER

#define PMC3_COUNTER   0x7FFFFFFF

PMC4_OV

#define PMC4_OV   0x80000000

PMC4_COUNTER

#define PMC4_COUNTER   0x7FFFFFFF

MMCR0_PMC1_HOLD

#define MMCR0_PMC1_HOLD   0x00000000

MMCR0_PMC1_CYCLE

#define MMCR0_PMC1_CYCLE   0x00000040

MMCR0_PMC1_INSTRUCTION

#define MMCR0_PMC1_INSTRUCTION   0x00000080

MMCR0_PMC1_TRANSITION

#define MMCR0_PMC1_TRANSITION   0x000000C0

MMCR0_PMC1_DISPATCHED

#define MMCR0_PMC1_DISPATCHED   0x00000100

MMCR0_PMC1_EIEIO

#define MMCR0_PMC1_EIEIO   0x00000140

MMCR0_PMC1_ITLB_CYCLE

#define MMCR0_PMC1_ITLB_CYCLE   0x00000180

MMCR0_PMC1_L2_HIT

#define MMCR0_PMC1_L2_HIT   0x000001C0

MMCR0_PMC1_EA

#define MMCR0_PMC1_EA   0x00000200

MMCR0_PMC1_IABR

#define MMCR0_PMC1_IABR   0x00000240

MMCR0_PMC1_L1_MISS

#define MMCR0_PMC1_L1_MISS   0x00000280

MMCR0_PMC1_Bx_UNRESOLVED

#define MMCR0_PMC1_Bx_UNRESOLVED   0x000002C0

MMCR0_PMC1_Bx_STALL_CYCLE

#define MMCR0_PMC1_Bx_STALL_CYCLE   0x00000300

MMCR0_PMC1_IC_FETCH_MISS

#define MMCR0_PMC1_IC_FETCH_MISS   0x00000340

MMCR0_PMC2_HOLD

#define MMCR0_PMC2_HOLD   0x00000000

MMCR0_PMC2_CYCLE

#define MMCR0_PMC2_CYCLE   0x00000001

MMCR0_PMC2_INSTRUCTION

#define MMCR0_PMC2_INSTRUCTION   0x00000002

MMCR0_PMC2_TRANSITION

#define MMCR0_PMC2_TRANSITION   0x00000003

MMCR0_PMC2_DISPATCHED

#define MMCR0_PMC2_DISPATCHED   0x00000004

MMCR0_PMC2_IC_MISS

#define MMCR0_PMC2_IC_MISS   0x00000005

MMCR0_PMC2_ITLB_MISS

#define MMCR0_PMC2_ITLB_MISS   0x00000006

MMCR0_PMC2_L2_I_MISS

#define MMCR0_PMC2_L2_I_MISS   0x00000007

MMCR0_PMC2_Bx_FALL_TROUGH

#define MMCR0_PMC2_Bx_FALL_TROUGH   0x00000008

MMCR0_PMC2_PR_SWITCH

#define MMCR0_PMC2_PR_SWITCH   0x00000009

MMCR0_PMC2_RESERVED_LOAD

#define MMCR0_PMC2_RESERVED_LOAD   0x0000000A

MMCR0_PMC2_LOAD_STORE

#define MMCR0_PMC2_LOAD_STORE   0x0000000B

MMCR0_PMC2_SNOOP

#define MMCR0_PMC2_SNOOP   0x0000000C

MMCR0_PMC2_L1_CASTOUT

#define MMCR0_PMC2_L1_CASTOUT   0x0000000D

MMCR0_PMC2_SYSTEM

#define MMCR0_PMC2_SYSTEM   0x0000000E

MMCR0_PMC2_IC_FETCH_MISS

#define MMCR0_PMC2_IC_FETCH_MISS   0x0000000F

MMCR0_PMC2_Bx_OUT_OF_ORDER

#define MMCR0_PMC2_Bx_OUT_OF_ORDER   0x00000010

MMCR1_PMC3_HOLD

#define MMCR1_PMC3_HOLD   0x00000000

MMCR1_PMC3_CYCLE

#define MMCR1_PMC3_CYCLE   0x08000000

MMCR1_PMC3_INSTRUCTION

#define MMCR1_PMC3_INSTRUCTION   0x10000000

MMCR1_PMC3_TRANSITION

#define MMCR1_PMC3_TRANSITION   0x18000000

MMCR1_PMC3_DISPATCHED

#define MMCR1_PMC3_DISPATCHED   0x20000000

MMCR1_PMC3_DC_MISS

#define MMCR1_PMC3_DC_MISS   0x28000000

MMCR1_PMC3_DTLB_MISS

#define MMCR1_PMC3_DTLB_MISS   0x30000000

MMCR1_PMC3_L2_D_MISS

#define MMCR1_PMC3_L2_D_MISS   0x38000000

MMCR1_PMC3_Bx_TAKEN

#define MMCR1_PMC3_Bx_TAKEN   0x40000000

MMCR1_PMC3_PM_SWITCH

#define MMCR1_PMC3_PM_SWITCH   0x48000000

MMCR1_PMC3_COND_STORE

#define MMCR1_PMC3_COND_STORE   0x50000000

MMCR1_PMC3_FPU

#define MMCR1_PMC3_FPU   0x58000000

MMCR1_PMC3_L2_SNOOP_CASTOUT

#define MMCR1_PMC3_L2_SNOOP_CASTOUT   0x60000000

MMCR1_PMC3_L2_HIT

#define MMCR1_PMC3_L2_HIT   0x68000000

MMCR1_PMC3_L1_MISS_CYCLE

#define MMCR1_PMC3_L1_MISS_CYCLE   0x78000000

MMCR1_PMC3_Bx_SECOND

#define MMCR1_PMC3_Bx_SECOND   0x80000000

MMCR1_PMC3_BPU_LR_CR

#define MMCR1_PMC3_BPU_LR_CR   0x88000000

MMCR1_PMC4_HOLD

#define MMCR1_PMC4_HOLD   0x00000000

MMCR1_PMC4_CYCLE

#define MMCR1_PMC4_CYCLE   0x00400000

MMCR1_PMC4_INSTRUCTION

#define MMCR1_PMC4_INSTRUCTION   0x00800000

MMCR1_PMC4_TRANSITION

#define MMCR1_PMC4_TRANSITION   0x00C00000

MMCR1_PMC4_DISPATCHED

#define MMCR1_PMC4_DISPATCHED   0x01000000

MMCR1_PMC4_L2_CASTOUT

#define MMCR1_PMC4_L2_CASTOUT   0x01400000

MMCR1_PMC4_DTLB_CYCLE

#define MMCR1_PMC4_DTLB_CYCLE   0x01800000

MMCR1_PMC4_Bx_MISSED

#define MMCR1_PMC4_Bx_MISSED   0x02000000

MMCR1_PMC4_COND_STORE_INT

#define MMCR1_PMC4_COND_STORE_INT   0x02800000

MMCR1_PMC4_SYNC

#define MMCR1_PMC4_SYNC   0x02C00000

MMCR1_PMC4_SNOOP_RETRY

#define MMCR1_PMC4_SNOOP_RETRY   0x03000000

MMCR1_PMC4_INTEGER

#define MMCR1_PMC4_INTEGER   0x03400000

MMCR1_PMC4_BPU_THIRD

#define MMCR1_PMC4_BPU_THIRD   0x03800000

MMCR1_PMC4_DC_MISS

#define MMCR1_PMC4_DC_MISS   0x07C00000

FPSCR_FX

#define FPSCR_FX   0x80000000

FPSCR_FEX

#define FPSCR_FEX   0x40000000

FPSCR_VX

#define FPSCR_VX   0x20000000

FPSCR_OX

#define FPSCR_OX   0x10000000

FPSCR_UX

#define FPSCR_UX   0x08000000

FPSCR_ZX

#define FPSCR_ZX   0x04000000

FPSCR_XX

#define FPSCR_XX   0x02000000

FPSCR_VXSNAN

#define FPSCR_VXSNAN   0x01000000

FPSCR_VXISI

#define FPSCR_VXISI   0x00800000

FPSCR_VXIDI

#define FPSCR_VXIDI   0x00400000

FPSCR_VXZDZ

#define FPSCR_VXZDZ   0x00200000

FPSCR_VXIMZ

#define FPSCR_VXIMZ   0x00100000

FPSCR_VXVC

#define FPSCR_VXVC   0x00080000

FPSCR_FR

#define FPSCR_FR   0x00040000

FPSCR_FI

#define FPSCR_FI   0x00020000

FPSCR_VXSOFT

#define FPSCR_VXSOFT   0x00000400

FPSCR_VXSQRT

#define FPSCR_VXSQRT   0x00000200

FPSCR_VXCVI

#define FPSCR_VXCVI   0x00000100

FPSCR_VE

#define FPSCR_VE   0x00000080

FPSCR_OE

#define FPSCR_OE   0x00000040

FPSCR_UE

#define FPSCR_UE   0x00000020

FPSCR_ZE

#define FPSCR_ZE   0x00000010

FPSCR_XE

#define FPSCR_XE   0x00000008

FPSCR_NI

#define FPSCR_NI   0x00000004

FPSCR_FX_BIT

#define FPSCR_FX_BIT   0

FPSCR_FEX_BIT

#define FPSCR_FEX_BIT   1

FPSCR_VX_BIT

#define FPSCR_VX_BIT   2

FPSCR_OX_BIT

#define FPSCR_OX_BIT   3

FPSCR_UX_BIT

#define FPSCR_UX_BIT   4

FPSCR_ZX_BIT

#define FPSCR_ZX_BIT   5

FPSCR_XX_BIT

#define FPSCR_XX_BIT   6

FPSCR_VXSNAN_BIT

#define FPSCR_VXSNAN_BIT   7

FPSCR_VXISI_BIT

#define FPSCR_VXISI_BIT   8

FPSCR_VXIDI_BIT

#define FPSCR_VXIDI_BIT   9

FPSCR_VXZDZ_BIT

#define FPSCR_VXZDZ_BIT   10

FPSCR_VXIMZ_BIT

#define FPSCR_VXIMZ_BIT   11

FPSCR_VXVC_BIT

#define FPSCR_VXVC_BIT   12

FPSCR_FR_BIT

#define FPSCR_FR_BIT   13

FPSCR_FI_BIT

#define FPSCR_FI_BIT   14

FPSCR_VXSOFT_BIT

#define FPSCR_VXSOFT_BIT   21

FPSCR_VXSQRT_BIT

#define FPSCR_VXSQRT_BIT   22

FPSCR_VXCVI_BIT

#define FPSCR_VXCVI_BIT   23

FPSCR_VE_BIT

#define FPSCR_VE_BIT   24

FPSCR_OE_BIT

#define FPSCR_OE_BIT   25

FPSCR_UE_BIT

#define FPSCR_UE_BIT   26

FPSCR_ZE_BIT

#define FPSCR_ZE_BIT   27

FPSCR_XE_BIT

#define FPSCR_XE_BIT   28

FPSCR_NI_BIT

#define FPSCR_NI_BIT   29

Function Documentation

PPCMfmsr()

u32 PPCMfmsr

(

)

PPCMtmsr()

void PPCMtmsr

(

u32

newMSR

)

PPCOrMsr()

u32 PPCOrMsr

(

u32

value

)

PPCMfhid0()

u32 PPCMfhid0

(

)

PPCMthid0()

void PPCMthid0

(

u32

newHID0

)

PPCMfl2cr()

u32 PPCMfl2cr

(

)

PPCMtl2cr()

void PPCMtl2cr

(

u32

newL2cr

)

PPCMtdec()

void PPCMtdec

(

u32

newDec

)

PPCSync()

void PPCSync

(

)

PPCHalt()

void PPCHalt

(

)

PPCMffpscr()

u32 PPCMffpscr

(

)

PPCMtfpscr()

void PPCMtfpscr

(

u32

newFPSCR

)

PPCMfhid2()

u32 PPCMfhid2

(

)

PPCMthid2()

void PPCMthid2

(

u32

newhid2

)

PPCMfwpar()

u32 PPCMfwpar

(

)

PPCMtwpar()

void PPCMtwpar

(

u32

newwpar

)

PPCEnableSpeculation()

void PPCEnableSpeculation

(

)

PPCDisableSpeculation()

void PPCDisableSpeculation

(

)

PPCSetFpIEEEMode()

void PPCSetFpIEEEMode

(

)

PPCSetFpNonIEEEMode()

void PPCSetFpNonIEEEMode

(

)

PPCMfpmc4()

u32 PPCMfpmc4

(

)

PPCMfpmc3()

u32 PPCMfpmc3

(

)

PPCMfpmc1()

u32 PPCMfpmc1

(

)

PPCMtpmc1()

void PPCMtpmc1

(

u32

newPmc1

)

PPCMtpmc2()

void PPCMtpmc2

(

u32

newPmc1

)

PPCMtpmc3()

void PPCMtpmc3

(

u32

newPmc1

)

PPCMtpmc4()

void PPCMtpmc4

(

u32

newPmc1

)

PPCMtmmcr0()

void PPCMtmmcr0

(

u32

newMmcr0

)

PPCMtmmcr1()

void PPCMtmmcr1

(

u32

newMmcr0

)

PPCMtdmaU()

void PPCMtdmaU

(

u32

newdmau

)

PPCMtdmaL()

void PPCMtdmaL

(

u32

newdmal

)

PPCMfdec()

u32 PPCMfdec

(

void

)

PPCAndMsr()

u32 PPCAndMsr

(

u32

value

)

PPCAndCMsr()

u32 PPCAndCMsr

(

u32

value

)

PPCMfhid1()

u32 PPCMfhid1

(

)

PPCEieio()

void PPCEieio

(

)

PPCMfmmcr0()

u32 PPCMfmmcr0

(

)

PPCMfmmcr1()

u32 PPCMfmmcr1

(

)

PPCMfpmc2()

u32 PPCMfpmc2

(

)

PPCMfsia()

u32 PPCMfsia

(

)

PPCMtsia()

void PPCMtsia

(

u32

newSia

)

PPCMfdmaL()

u32 PPCMfdmaL

(

)

PPCMfpvr()

u32 PPCMfpvr

(

)

PPCMfdmaU()

u32 PPCMfdmaU

(

)

PMBegin()

void PMBegin

(

void

)

PMEnd()

void PMEnd

(

void

)

PMCycles()

void PMCycles

(

void

)

PML1FetchMisses()

void PML1FetchMisses

(

void

)

PML1MissCycles()

void PML1MissCycles

(

void

)

PMInstructions()

void PMInstructions

(

void

)